This invention relates generally to semiconductor memory devices. In particular, the present invention is concerned with a block oriented random access memory (BORAM) having improved addressing of individual blocks of the memory.
Block oriented random access memories have application in large memory systems in which individual blocks of the memory are randomly accessed. All of the data within the block is then written or read out in a given order. BORAMs have been designated as a means of reducing the expense of randomly accessed read/write memories and as a means of achieving faster read and write times.
U.S. Pats. Nos. 3,895,360 by Cricchi et al. and 3,898,632 by Spencer describe integrated circuit memory devices for use in a block oriented random access memory. In these prior art BORAMs, addressing of an N .times. M memory array is accomplished by using log.sub.2 N input lines. The addressing of the memory array is provided by an address buffer and a word decoder, which converts the log.sub.2 N signals into N addresses for the N .times. M memory array.
These prior art devices have several disadvantages as a result of the addressing system which they use. First, they require a large number of input pins (a total of log.sub.2 N + 2) in order to address, load the buffer, and select a particular chip. Additional input/output pins increase the cost of the integrated circuit package and the assembly cost at both the integrated circuit and system levels. Second, the address buffer and word decorder require a considerable amount of space on the integrated circuit chip.